ภาพปกงานวิจัย Adaptive Equalization Architecture Using Distributed Arithmetic for Partial Response Channels
ปีที่ตีพิมพ์ 2553
เอกสารประกอบ ดาวน์โหลด
จำนวนเข้าชม 1

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA) which is able to calculate the inner product by shifting and accumulating of partial products and storing in look-up table also the desired adaptive digital filter will be multiplierless filter. In addition the hardware implementation uses VHDL (Very high-speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter

APA

Chivapreecha, Sorawat. Dejhan, Kobchai. Jaruvarakul, Aungkana. Jaruvarakul, Nivat. ( 2553 ). Adaptive Equalization Architecture Using Distributed Arithmetic for Partial Response Channels. กรุงเทพมหานคร.

Chicago

Chivapreecha, Sorawat. Dejhan, Kobchai. Jaruvarakul, Aungkana. Jaruvarakul, Nivat. Adaptive Equalization Architecture Using Distributed Arithmetic for Partial Response Channels. กรุงเทพมหานคร: มหาวิทยาลัยเทคโนโลยีราชมงคลพระนคร, 2553.

MLA

Chivapreecha, Sorawat. Dejhan, Kobchai. Jaruvarakul, Aungkana. Jaruvarakul, Nivat. Adaptive Equalization Architecture Using Distributed Arithmetic for Partial Response Channels. กรุงเทพมหานคร, 2553.

Vancouver

Chivapreecha, Sorawat. Dejhan, Kobchai. Jaruvarakul, Aungkana. Jaruvarakul, Nivat. Adaptive Equalization Architecture Using Distributed Arithmetic for Partial Response Channels. กรุงเทพมหานคร; 2553.