In FinFET-based VLSI designs heat issues from increase of driving current with temperature and self-heating effect profoundly influence the circuit performance and reliability. This work evaluates the performance of FinFET-based combinational circuits considering BTI stress and thermal effect of supply voltage and frequency variations. The proposed simulation framework is applied to selected benchmark circuits implemented with the 14-nm tri-gate bulk FinFET technology. The experimental results reveal that as temperature increases BTI aging delay increasingly worsens yet it is overridden by performance gain from the increase in driving current. We also prove that BTI degradation is dependent on power supply and frequency through their thermal impacts. Further we introduce a DVFS based power reduction approach that scales down the supply voltage of hot circuits to maintain the performance. The results show that power reduction yielded from the proposed technique is larger for all circuits working at higher ambient temperature (as large as 66% in some experimental circuits working at 20 oC above the baseline ambient temperature) with a slight decrease in BTI degradation.

For modern processors permanent and transient errors due to increased temperature and single event effect continue to intensify as device technologies scale down to small nanometers. While many researchers have proposed efficient methods to limit one of these two problems those techniques may worsen the other reliability aspect. In this project we introduce a novel leakage reduction approach for long-term reliability improvement which considers the impact of shortterm reliability effect from soft errors. In particular we firstly employ body bias tuning to reduce leakage and further investigate its impact on delay and soft error rate of the circuit. It has been discovered from our experiment that use of reverse body bias to control leakage can raise the soft error rate in addition to the delay performance. We therefore integrate several effects of body bias into the proposed leakage reduction technique. The experimental results show that our approach provides satisfactory leakage reduction with confined soft error and delay degradation in 32 nm high-k/metal gate benchmark circuits.