This thesis presented the design and construction of an adaptive active band-pass filter by using a tachometer circuit. The main part was the multi voltage-mode filter circuit based on an operational transconductance amplifier which could automatically adjust the center frequency to adapt to the input signal frequency by the tachometer circuit. The frequency error value in the center frequency was set to be ≤ 3% of the input signal. Furthermore the proposed filter could support the input signal in the frequency range of 10 Hz - 10 kHz. From the simulation and experimental results of the proposed prototype filter it could respond to the frequency according to the theory of the band-pass filter and the error in choosing the center frequency which was 1.45 % and 2.6 % respectively (below the set error value of 3 %). Therefore the proposed filter could be used for real application. The working principles of the proposed prototype filter could also be applied to the noise attenuation circuit of an electrocardiogram machine. Moreover this research could be used as a guideline study for those who want to develop other types of adaptive active filters for higher efficiency.

Using copper wire instead of gold wire can reduce a lot of cost in IC production of semiconductor industrial. However the circuit stability (Circuit Reliability) is less than the use of goal wire. Therefore the study to improve the production of integrated circuits in the part of the wire bonding process by increasing the baking process. It is an important process to improve the quality of the integrated circuit between Cu wire and chip. For this experimental study of baking process it was performed by comparing IMC values at 175 ˚C and 200 ˚C. The quality of workpiece was tested and measured by Scanning Electron Microscope (SEM) machine every 30 minutes. The research experiment found that the temperature with effect to the workpiece quality to stabilize the IMC value was 175 ˚C for 9 hours nevertheless the new temperature at 200 ˚C it has been applied with only 3 hours. Finally the IMC testing result is higher than the average of the at 60% standard acceptable level as other research reviews and it also higher than the acceptable level of the industry level at 80%. Hence this result can reduce time cost of IC and workpieces production and it also including the higher quality of the products.

Fin Field Effect Transistor (FinFET) technology has increasingly been adopted for use within integrated circuits thanks to its superior electrical integrity and scalability. However a steady increase in vulnerability of FinFET circuits to negative bias temperature instability (NBTI) has recently become one of the major lifetime reliability problems. In this paper we propose a simulation framework to address NBTI in combinational circuits implemented with 14-nm tri-gate FinFET predictive technology. Particle swarm optimization (PSO) algorithm is applied to construct an accurate long-term NBTI degradation model from cycle-by-cycle data history. The proposed simulation methodology provides accurate results with high efficacy in computation time compared to reference models. From the proposed framework the average delay degradation for all experimental circuits under normal operation after 10-year NBTI stress is approximately 6% yet temperature variation in the circuit strongly influences NBTI degradation.

For modern processors two reliability issues namely increased leakage power and soft error rate continue to intensify as device technologies scale down to nanometers. While many researchers have proposed methods to efficiently control leakage power by tuning body bias few recent works have considered the quantitative negative impact of this technique on circuit soft error vulnerability. In this paper we introduce a novel body bias based approach for reliability improvement that correlates leakage reduction and soft error immunity degradation. The experimental results show that the proposed technique provides satisfactory leakage reduction with confined soft error degradation in 32 nm high-k/metal gate benchmark circuits.