For modern processors two reliability issues namely increased leakage power and soft error rate continue to intensify as device technologies scale down to nanometers. While many researchers have proposed methods to efficiently control leakage power by tuning body bias few recent works have considered the quantitative negative impact of this technique on circuit soft error vulnerability. In this paper we introduce a novel body bias based approach for reliability improvement that correlates leakage reduction and soft error immunity degradation. The experimental results show that the proposed technique provides satisfactory leakage reduction with confined soft error degradation in 32 nm high-k/metal gate benchmark circuits.

For modern processors permanent and transient errors due to increased temperature and single event effect continue to intensify as device technologies scale down to small nanometers. While many researchers have proposed efficient methods to limit one of these two problems those techniques may worsen the other reliability aspect. In this project we introduce a novel leakage reduction approach for long-term reliability improvement which considers the impact of shortterm reliability effect from soft errors. In particular we firstly employ body bias tuning to reduce leakage and further investigate its impact on delay and soft error rate of the circuit. It has been discovered from our experiment that use of reverse body bias to control leakage can raise the soft error rate in addition to the delay performance. We therefore integrate several effects of body bias into the proposed leakage reduction technique. The experimental results show that our approach provides satisfactory leakage reduction with confined soft error and delay degradation in 32 nm high-k/metal gate benchmark circuits.