In FinFET-based VLSI designs heat issues from increase of driving current with temperature and self-heating effect profoundly influence the circuit performance and reliability. This work evaluates the performance of FinFET-based combinational circuits considering BTI stress and thermal effect of supply voltage and frequency variations. The proposed simulation framework is applied to selected benchmark circuits implemented with the 14-nm tri-gate bulk FinFET technology. The experimental results reveal that as temperature increases BTI aging delay increasingly worsens yet it is overridden by performance gain from the increase in driving current. We also prove that BTI degradation is dependent on power supply and frequency through their thermal impacts. Further we introduce a DVFS based power reduction approach that scales down the supply voltage of hot circuits to maintain the performance. The results show that power reduction yielded from the proposed technique is larger for all circuits working at higher ambient temperature (as large as 66% in some experimental circuits working at 20 oC above the baseline ambient temperature) with a slight decrease in BTI degradation.

For modern processors permanent and transient errors due to increased temperature and single event effect continue to intensify as device technologies scale down to small nanometers. While many researchers have proposed efficient methods to limit one of these two problems those techniques may worsen the other reliability aspect. In this project we introduce a novel leakage reduction approach for long-term reliability improvement which considers the impact of shortterm reliability effect from soft errors. In particular we firstly employ body bias tuning to reduce leakage and further investigate its impact on delay and soft error rate of the circuit. It has been discovered from our experiment that use of reverse body bias to control leakage can raise the soft error rate in addition to the delay performance. We therefore integrate several effects of body bias into the proposed leakage reduction technique. The experimental results show that our approach provides satisfactory leakage reduction with confined soft error and delay degradation in 32 nm high-k/metal gate benchmark circuits.

Fin Field Effect Transistor (FinFET) technology has increasingly been adopted for use within integrated circuits thanks to its superior electrical integrity and scalability. However a steady increase in vulnerability of FinFET circuits to negative bias temperature instability (NBTI) has recently become one of the major lifetime reliability problems. In this paper we propose a simulation framework to address NBTI in combinational circuits implemented with 14-nm tri-gate FinFET predictive technology. Particle swarm optimization (PSO) algorithm is applied to construct an accurate long-term NBTI degradation model from cycle-by-cycle data history. The proposed simulation methodology provides accurate results with high efficacy in computation time compared to reference models. From the proposed framework the average delay degradation for all experimental circuits under normal operation after 10-year NBTI stress is approximately 6% yet temperature variation in the circuit strongly influences NBTI degradation.

For modern processors two reliability issues namely increased leakage power and soft error rate continue to intensify as device technologies scale down to nanometers. While many researchers have proposed methods to efficiently control leakage power by tuning body bias few recent works have considered the quantitative negative impact of this technique on circuit soft error vulnerability. In this paper we introduce a novel body bias based approach for reliability improvement that correlates leakage reduction and soft error immunity degradation. The experimental results show that the proposed technique provides satisfactory leakage reduction with confined soft error degradation in 32 nm high-k/metal gate benchmark circuits.

This article describes an efficient approach to the implementation of bit-serial lattice wave digital filters based on field programmable gate array (FPGA). In this paper a time schedule of all of the bit-serial two-port adaptors is presented as a bridge between conception and completion. Finally with the satisfying frequency response the filter is successfully tested by both computer simulation and real signal measured from the programmed FPGA.